00001 /****************************************************************************** 00002 * 00003 * $RCSfile$ 00004 * $Revision$ 00005 * 00006 * This module provides the interface definitions for setting up and 00007 * controlling the various interrupt modes present on the ARM processor. 00008 * Copyright 2004, R O SoftWare 00009 * No guarantees, warrantees, or promises, implied or otherwise. 00010 * May be used for hobby or commercial purposes provided copyright 00011 * notice remains intact. 00012 * 00013 *****************************************************************************/ 00014 #ifndef INC_ARM_VIC_H 00015 #define INC_ARM_VIC_H 00016 00017 #define __VIC_CNTL(idx) VICVectCntl##idx 00018 #define __VIC_ADDR(idx) VICVectAddr##idx 00019 #define _VIC_CNTL(idx) __VIC_CNTL(idx) 00020 #define _VIC_ADDR(idx) __VIC_ADDR(idx) 00021 00022 00023 /****************************************************************************** 00024 * 00025 * MACRO Name: ISR_ENTRY() 00026 * 00027 * Description: 00028 * This MACRO is used upon entry to an ISR. The current version of 00029 * the gcc compiler for ARM does not produce correct code for 00030 * interrupt routines to operate properly with THUMB code. The MACRO 00031 * performs the following steps: 00032 * 00033 * 1 - Adjust address at which execution should resume after servicing 00034 * ISR to compensate for IRQ entry 00035 * 2 - Save the non-banked registers r0-r12 and lr onto the IRQ stack. 00036 * 3 - Get the status of the interrupted program is in SPSR. 00037 * 4 - Push it onto the IRQ stack as well. 00038 * 00039 *****************************************************************************/ 00040 #define ISR_ENTRY() asm volatile(" sub lr, lr,#4\n" \ 00041 " stmfd sp!,{r0-r12,lr}\n" \ 00042 " mrs r1, spsr\n" \ 00043 " stmfd sp!,{r1}") 00044 00045 /****************************************************************************** 00046 * 00047 * MACRO Name: ISR_EXIT() 00048 * 00049 * Description: 00050 * This MACRO is used to exit an ISR. The current version of the gcc 00051 * compiler for ARM does not produce correct code for interrupt 00052 * routines to operate properly with THUMB code. The MACRO performs 00053 * the following steps: 00054 * 00055 * 1 - Recover SPSR value from stack 00056 * 2 - and restore its value 00057 * 3 - Pop the return address & the saved general registers from 00058 * the IRQ stack & return 00059 * 00060 *****************************************************************************/ 00061 #define ISR_EXIT() asm volatile(" ldmfd sp!,{r1}\n" \ 00062 " msr spsr_c,r1\n" \ 00063 " ldmfd sp!,{r0-r12,pc}^") 00064 00065 /****************************************************************************** 00066 * 00067 * Function Name: disableIRQ() 00068 * 00069 * Description: 00070 * This function sets the IRQ disable bit in the status register 00071 * 00072 * Calling Sequence: 00073 * void 00074 * 00075 * Returns: 00076 * previous value of CPSR 00077 * 00078 *****************************************************************************/ 00079 unsigned disableIRQ(void); 00080 00081 /****************************************************************************** 00082 * 00083 * Function Name: enableIRQ() 00084 * 00085 * Description: 00086 * This function clears the IRQ disable bit in the status register 00087 * 00088 * Calling Sequence: 00089 * void 00090 * 00091 * Returns: 00092 * previous value of CPSR 00093 * 00094 *****************************************************************************/ 00095 unsigned enableIRQ(void); 00096 00097 /****************************************************************************** 00098 * 00099 * Function Name: restoreIRQ() 00100 * 00101 * Description: 00102 * This function restores the IRQ disable bit in the status register 00103 * to the value contained within passed oldCPSR 00104 * 00105 * Calling Sequence: 00106 * void 00107 * 00108 * Returns: 00109 * previous value of CPSR 00110 * 00111 *****************************************************************************/ 00112 unsigned restoreIRQ(unsigned oldCPSR); 00113 00114 /****************************************************************************** 00115 * 00116 * Function Name: disableFIQ() 00117 * 00118 * Description: 00119 * This function sets the FIQ disable bit in the status register 00120 * 00121 * Calling Sequence: 00122 * void 00123 * 00124 * Returns: 00125 * previous value of CPSR 00126 * 00127 *****************************************************************************/ 00128 unsigned disableFIQ(void); 00129 00130 /****************************************************************************** 00131 * 00132 * Function Name: enableFIQ() 00133 * 00134 * Description: 00135 * This function clears the FIQ disable bit in the status register 00136 * 00137 * Calling Sequence: 00138 * void 00139 * 00140 * Returns: 00141 * previous value of CPSR 00142 * 00143 *****************************************************************************/ 00144 unsigned enableFIQ(void); 00145 00146 /****************************************************************************** 00147 * 00148 * Function Name: restoreIRQ() 00149 * 00150 * Description: 00151 * This function restores the FIQ disable bit in the status register 00152 * to the value contained within passed oldCPSR 00153 * 00154 * Calling Sequence: 00155 * void 00156 * 00157 * Returns: 00158 * previous value of CPSR 00159 * 00160 *****************************************************************************/ 00161 unsigned restoreFIQ(unsigned oldCPSR); 00162 00163 #endif