00001 #ifndef HARDWARE_H
00002 #define HARDWARE_H
00003
00004
00005 #define RGB16bpp(r,g,b) \
00006 ((g & 0x7) << 5 | (b & 0x1f)) << 8 | (((r & 0x1f) <<3) | ((g & 0x38)>>3))
00007
00008
00009
00010
00011
00012
00013
00014
00015
00016 #define RGB16bpp1(r,g,b) \
00017 ((r & 0x7) << 5 | (g & 0x1f))
00018
00019 #define RGB16bpp2(r,g,b) \
00020 (((b & 0x1f) <<3) | ((r & 0x38)>>3))
00021
00022 typedef struct
00023 {
00024 unsigned char r;
00025 unsigned char g;
00026 unsigned char b;
00027 } SSDRGBType;
00028
00029 typedef struct
00030 {
00031 unsigned char r;
00032 unsigned char g;
00033 unsigned char b;
00034 unsigned char a;
00035 } SSDRGBAType;
00036
00037 #define MakeRGB16bpp(rgb) RGB16bpp(rgb.r, rgb.g, rgb.b)
00038
00039 #define MODE_2D_16bpp 0x0
00040 #define MODE_2D_32bpp 0x1
00041 #define MODE_2D_YUV 0x2
00042 #define MODE_2D_1bpp 0x4
00043 #define MODE_2D_8bpp 0x5
00044
00045 #define REG_DISP_BUFFER_SIZE 0x01
00046 #define REG_CONFIG_READBACK 0x02
00047 #define REG_REVISION_CODE 0x03
00048 #define REG_MEMCLK_CONFIG 0x04
00049 #define REG_PCLK_CONFIG 0x05
00050 #define REG_VCLK_CONFIG_0 0x06
00051 #define REG_VCLK_CONFIG_1 0x07
00052 #define REG_LUT_BLUE_WRITE_DATA 0x08
00053 #define REG_LUT_GREEN_WRITE_DATA 0x09
00054 #define REG_LUT_RED_WRITE_DATA 0x0a
00055 #define REG_LUT_WRITE_ADDR 0x0b
00056 #define REG_LUT_BLUE_READ_DATA 0x0c
00057 #define REG_LUT_GREEN_READ_DATA 0x0d
00058 #define REG_LUT_RED_READ_DATA 0x0e
00059 #define REG_LUT_READ_ADDR 0x0f
00060 #define REG_PANEL_TYPE 0x10
00061 #define REG_MOD_RATE 0x11
00062 #define REG_HORIZ_TOTAL_0 0x12
00063 #define REG_HORIZ_TOTAL_1 0x13
00064 #define REG_HDP 0x14
00065 #define REG_HDP_START_POS0 0x16
00066 #define REG_HDP_START_POS1 0x17
00067 #define REG_VERT_TOTAL0 0x18
00068 #define REG_VERT_TOTAL1 0x19
00069 #define REG_VDP0 0x1c
00070 #define REG_VDP1 0x1d
00071 #define REG_VDP_START_POS0 0x1e
00072 #define REG_VDP_START_POS1 0x1f
00073 #define REG_HSYNC_PULSE_WIDTH 0x20
00074 #define REG_LLINE_PULSE_START_SUBPIXEL_POS 0x21
00075 #define REG_HSYNC_PULSE_START_POS0 0x22
00076 #define REG_HSYNC_PULSE_START_POS1 0x23
00077 #define REG_VSYNC_PULSE_WIDTH 0x24
00078 #define REG_VSYNC_PULSE_START_POS0 0x26
00079 #define REG_VSYNC_PULSE_START_POS1 0x27
00080
00081 #define REG_FPFRAME_START_OFFSET0 0x30
00082 #define REG_FPFRAME_START_OFFSET1 0x31
00083 #define REG_FPFRAME_STOP_OFFSET0 0x34
00084 #define REG_FPFRAME_STOP_OFFSET1 0x35
00085 #define REG_HRTFT_SPECIAL_OUTPUT 0x38
00086 #define REG_GPIO1_PULSE_START 0x3c
00087 #define REG_GPIO1_PULSE_STOP 0x3e
00088 #define REG_GPIO2_PULSE_DELAY 0x40
00089 #define REG_LCD_SUBPIXEL_ALIGNMENT 0x42
00090 #define REG_STN_COLOR_DEPTH 0x45
00091
00092 #define REG_INTERRUPT_FLAG 0x48
00093 #define REG_INTERRUPT_ENABLE 0x4A
00094
00095 #define REG_DYN_DITHER_CONTROL 0x50
00096
00097 #define REG_DISPLAY_MODE 0x70
00098 #define REG_SPECIAL_EFFECTS 0x71
00099 #define REG_MAIN_WIN_DISP_START_ADDR0 0x74
00100 #define REG_MAIN_WIN_DISP_START_ADDR1 0x75
00101 #define REG_MAIN_WIN_DISP_START_ADDR2 0x76
00102 #define REG_MAIN_WIN_ADDR_OFFSET0 0x78
00103 #define REG_MAIN_WIN_ADDR_OFFSET1 0x79
00104 #define REG_FLOAT_WIN_DISP_START_ADDR0 0x7c
00105 #define REG_FLOAT_WIN_DISP_START_ADDR1 0x7d
00106 #define REG_FLOAT_WIN_DISP_START_ADDR2 0x7e
00107 #define REG_FLOAT_WIN_ADDR_OFFSET0 0x80
00108 #define REG_FLOAT_WIN_ADDR_OFFSET1 0x81
00109 #define REG_FLOAT_WIN_X_START_POS0 0x84
00110 #define REG_FLOAT_WIN_X_START_POS1 0x85
00111 #define REG_FLOAT_WIN_Y_START_POS0 0x88
00112 #define REG_FLOAT_WIN_Y_START_POS1 0x89
00113 #define REG_FLOAT_WIN_X_END_POS0 0x8c
00114 #define REG_FLOAT_WIN_X_END_POS1 0x8d
00115 #define REG_FLOAT_WIN_Y_END_POS0 0x90
00116 #define REG_FLOAT_WIN_Y_END_POS1 0x91
00117 #define REG_POWER_SAVE_CONFIG 0xa0
00118 #define REG_SOFTWARE_RESET 0xa2
00119 #define REG_SCRATCH_PAD0 0xa4
00120 #define REG_SCRATCH_PAD1 0xa5
00121 #define REG_GPIO_CONFIG0 0xa8
00122 #define REG_GPIO_CONFIG1 0xa9
00123 #define REG_GPIO_STATUS_CONTROL0 0xac
00124 #define REG_GPIO_STATUS_CONTROL1 0xad
00125 #define REG_PWM_CV_CLOCK_CONTROL 0xb0
00126 #define REG_PWM_CV_CLOCK_CONFIG 0xb1
00127 #define REG_CV_CLOCK_BURST_LENGTH 0xb2
00128 #define REG_PWM_CLOCK_DUTY_CYCLE 0xb3
00129
00130 #define REG_PWM1_CLOCK_CONTROL 0xb4
00131 #define REG_PWM1_CLOCK_CONFIG 0xb5
00132 #define REG_PWM1_CLOCK_DUTY_CYCLE 0xb7
00133
00134 #define REG_PWM2_CLOCK_CONTROL 0xb8
00135 #define REG_PWM2_CLOCK_CONFIG 0xb9
00136 #define REG_PWM2_CLOCK_DUTY_CYCLE 0xbb
00137
00138 #define REG_PWM3_CLOCK_CONTROL 0xbc
00139 #define REG_PWM3_CLOCK_CONFIG 0xbd
00140 #define REG_PWM3_CLOCK_DUTY_CYCLE 0xbf
00141
00142 #define CURSOR_NORMAL 0x00
00143 #define CURSOR_INVERT 0xaa
00144
00145 #define REG_CURSOR_FEATURE 0xc0
00146 #define REG_CURSOR1_BLINK_TOTAL0 0xc4
00147 #define REG_CURSOR1_BLINK_TOTAL1 0xc5
00148 #define REG_CURSOR1_BLINK_ON0 0xc8
00149 #define REG_CURSOR1_BLINK_ON1 0xc9
00150 #define REG_CURSOR1_MEM_START0 0xcc
00151 #define REG_CURSOR1_MEM_START1 0xcd
00152 #define REG_CURSOR1_MEM_START2 0xce
00153 #define REG_CURSOR1_POSX0 0xd0
00154 #define REG_CURSOR1_POSX1 0xd1
00155 #define REG_CURSOR1_POSY0 0xd4
00156 #define REG_CURSOR1_POSY1 0xd5
00157 #define REG_CURSOR1_HORIZ_SIZE_0 0xd8
00158 #define REG_CURSOR1_HORIZ_SIZE_1 0xd9
00159 #define REG_CURSOR1_VERT_SIZE_0 0xdc
00160 #define REG_CURSOR1_VERT_SIZE_1 0xdd
00161 #define REG_CURSOR1_COL_IND1_0 0xe0
00162 #define REG_CURSOR1_COL_IND1_1 0xe1
00163 #define REG_CURSOR1_COL_IND1_2 0xe2
00164 #define REG_CURSOR1_COL_IND1_3 0xe3
00165 #define REG_CURSOR1_COL_IND2_0 0xe4
00166 #define REG_CURSOR1_COL_IND2_1 0xe5
00167 #define REG_CURSOR1_COL_IND2_2 0xe6
00168 #define REG_CURSOR1_COL_IND2_3 0xe7
00169 #define REG_CURSOR1_COL_IND3_0 0xe8
00170 #define REG_CURSOR1_COL_IND3_1 0xe9
00171 #define REG_CURSOR1_COL_IND3_2 0xea
00172 #define REG_CURSOR1_COL_IND3_3 0xeb
00173 #define REG_CURSOR2_BLINK_TOTAL0 0xec
00174 #define REG_CURSOR2_BLINK_TOTAL1 0xed
00175 #define REG_CURSOR2_BLINK_ON0 0xf0
00176 #define REG_CURSOR2_BLINK_ON1 0xf1
00177 #define REG_CURSOR2_MEM_START0 0xf4
00178 #define REG_CURSOR2_MEM_START1 0xf5
00179 #define REG_CURSOR2_MEM_START2 0xf6
00180 #define REG_CURSOR2_POSX0 0xf8
00181 #define REG_CURSOR2_POSX1 0xf9
00182 #define REG_CURSOR2_POSY0 0xfc
00183 #define REG_CURSOR2_POSY1 0xfd
00184 #define REG_CURSOR2_HORIZ_SIZE_0 0x100
00185 #define REG_CURSOR2_HORIZ_SIZE_1 0x101
00186 #define REG_CURSOR2_VERT_SIZE_0 0x104
00187 #define REG_CURSOR2_VERT_SIZE_1 0x105
00188 #define REG_CURSOR2_COL_IND1_0 0x108
00189 #define REG_CURSOR2_COL_IND1_1 0x109
00190 #define REG_CURSOR2_COL_IND1_2 0x10a
00191 #define REG_CURSOR2_COL_IND1_3 0x10b
00192 #define REG_CURSOR2_COL_IND2_0 0x10c
00193 #define REG_CURSOR2_COL_IND2_1 0x10d
00194 #define REG_CURSOR2_COL_IND2_2 0x10e
00195 #define REG_CURSOR2_COL_IND2_3 0x10f
00196 #define REG_CURSOR2_COL_IND3_0 0x110
00197 #define REG_CURSOR2_COL_IND3_1 0x111
00198 #define REG_CURSOR2_COL_IND3_2 0x112
00199 #define REG_CURSOR2_COL_IND3_3 0x113
00200
00201 #define REG_PLL_CLK_SET_0 0x126
00202 #define REG_PLL_CLK_SET_1 0x127
00203 #define REG_PLL_CLK_SET_2 0x12B
00204
00205 #define REG_MAIN_REFLESH 0x12c
00206
00207 #define REG_PCLK_FREQ_RATIO_0 0x158
00208 #define REG_PCLK_FREQ_RATIO_1 0x159
00209 #define REG_PCLK_FREQ_RATIO_2 0x15a
00210
00211 #define REG_DV_OP_MODE 0x160
00212 #define REG_DV_FRAME_SAMPLING 0x161
00213
00214 #define REG_DV_NFRAME_POS_0 0x162
00215 #define REG_DV_NFRAME_POS_1 0x163
00216 #define REG_DV_JHORI_SIZE_0 0x164
00217 #define REG_DV_JHORI_SIZE_1 0x165
00218 #define REG_DV_JVERT_SIZE_0 0x168
00219 #define REG_DV_JVERT_SIZE_1 0x169
00220
00221
00222 #define REG_DV_JMEM_STR_0 0x16c
00223 #define REG_DV_JMEM_STR_1 0x16d
00224 #define REG_DV_JMEM_STR_2 0x16e
00225 #define REG_DV_JMEM_STR_3 0x16f
00226
00227 #define REG_DV_VHDEC_RATIO 0x170
00228 #define REG_DV_VVDEC_RATIO 0x171
00229 #define REG_DV_JHDEC_RATIO 0x172
00230 #define REG_DV_JVDEC_RATIO 0x173
00231
00232 #define REG_DV_HORI_PERIOD_0 0x174
00233 #define REG_DV_HORI_PERIOD_1 0x175
00234
00235 #define REG_DV_HORI_MAX_0 0x17c
00236 #define REG_DV_HORI_MAX_1 0x17d
00237
00238 #define REG_DV_VERT_MAX_0 0x180
00239 #define REG_DV_VERT_MAX_1 0x181
00240
00241 #define REG_DV_HCROP_STR_0 0x184
00242 #define REG_DV_HCROP_STR_1 0x185
00243
00244 #define REG_DV_VCROP_STR_0 0x188
00245 #define REG_DV_VCROP_STR_1 0x189
00246
00247 #define REG_DV_HCROP_SIZE_0 0x18c
00248 #define REG_DV_HCROP_SIZE_1 0x18d
00249
00250 #define REG_DV_VCROP_SIZE_0 0x190
00251 #define REG_DV_VCROP_SIZE_1 0x191
00252
00253 #define REG_DV_FRAME_PULSE_WIDTH 0x194
00254 #if 0
00255 #define REG_DV_VHORI_SIZE_0 0x194
00256 #define REG_DV_VHORI_SIZE_1 0x195
00257 #define REG_DV_VVERT_SIZE_0 0x198
00258 #define REG_DV_VVERT_SIZE_1 0x199
00259 #endif
00260
00261 #define REG_DV_VMEM_STR_ADDR1_0 0x19c
00262 #define REG_DV_VMEM_STR_ADDR1_1 0x19d
00263 #define REG_DV_VMEM_STR_ADDR1_2 0x19e
00264 #define REG_DV_VMEM_STR_ADDR1_3 0x19f
00265
00266 #define REG_DV_VMEM_STR_ADDR2_0 0x1a0
00267 #define REG_DV_VMEM_STR_ADDR2_1 0x1a1
00268 #define REG_DV_VMEM_STR_ADDR2_2 0x1a2
00269 #define REG_DV_VMEM_STR_ADDR2_3 0x1a3
00270
00271 #define REG_DV_OFORMAT 0x1a4
00272 #define REG_DV_ALPHA 0x1a5
00273 #define REG_DV_SUBPIXEL_MODE 0x1a5
00274 #define REG_DV_CSC_MODE 0x1a8
00275 #define REG_DV_Y 0x1a9
00276 #define REG_DV_CB 0x1aa
00277 #define REG_DV_CR 0x1ab
00278
00279 #define REG_DV_TV_0 0x1ac
00280 #define REG_DV_TV_1 0x1ad
00281 #define REG_DV_TV_2 0x1ae
00282
00283 #define REG_DV_ENB 0x1af
00284
00285 #define REG_DV_DV0_START_ADDR_0 0x1b0
00286 #define REG_DV_DV0_START_ADDR_1 0x1b1
00287 #define REG_DV_DV0_START_ADDR_2 0x1b2
00288
00289 #define REG_DV_DV1_START_ADDR_0 0x1b4
00290 #define REG_DV_DV1_START_ADDR_1 0x1b5
00291 #define REG_DV_DV1_START_ADDR_2 0x1b6
00292
00293 #define REG_2D_1d0 0x1d0
00294 #define REG_2D_1d1 0x1d1
00295 #define REG_2D_1d2 0x1d2
00296 #define REG_2D_1d4 0x1d4
00297 #define REG_2D_1d5 0x1d5
00298 #define REG_2D_1d6 0x1d6
00299 #define REG_2D_1d8 0x1d8
00300 #define REG_2D_1d9 0x1d9
00301 #define REG_2D_1dc 0x1dc
00302 #define REG_2D_1dd 0x1dd
00303 #define REG_2D_1de 0x1de
00304 #define REG_2D_1e4 0x1e4
00305 #define REG_2D_1e5 0x1e5
00306 #define REG_2D_1e8 0x1e8
00307 #define REG_2D_1e9 0x1e9
00308 #define REG_2D_1ec 0x1ec
00309 #define REG_2D_1ed 0x1ed
00310 #define REG_2D_1f0 0x1f0
00311 #define REG_2D_1f1 0x1f1
00312 #define REG_2D_1f4 0x1f4
00313 #define REG_2D_1f5 0x1f5
00314 #define REG_2D_1f6 0x1f6
00315 #define REG_2D_1f8 0x1f8
00316 #define REG_2D_1f9 0x1f9
00317 #define REG_2D_1fc 0x1fc
00318 #define REG_2D_1fd 0x1fd
00319 #define REG_2D_1fe 0x1fe
00320 #define REG_2D_204 0x204
00321 #define REG_2D_205 0x205
00322 #define REG_2D_206 0x206
00323 #define REG_2D_208 0x208
00324 #define REG_2D_209 0x209
00325 #define REG_2D_214 0x214
00326 #define REG_2D_215 0x215
00327 #define REG_2D_218 0x218
00328 #define REG_2D_219 0x219
00329 #define REG_2D_220 0x220
00330
00331 #define REG_2D_CMD_1 0x1d0
00332 #define REG_2D_CMD_2 0x1d1
00333 #define REG_2D_CMD_FIFO_STATUS 0x1d2
00334 #define REG_2D_SRC_WND_START_ADDR0 0x1d4
00335 #define REG_2D_SRC_WND_START_ADDR1 0x1d5
00336 #define REG_2D_SRC_WND_START_ADDR2 0x1d6
00337 #define REG_2D_SRC_WND_ADDR_OFFSET0 0x1d8
00338 #define REG_2D_SRC_WND_ADDR_OFFSET1 0x1d9
00339 #define REG_2D_SRC_WND_COLOR_MODE 0x1dc
00340 #define REG_2D_DEST_WND_COLOR_MODE 0x1dd
00341 #define REG_2D_SRC_WND_WIDTH0 0x1e4
00342 #define REG_2D_SRC_WND_WIDTH1 0x1e5
00343 #define REG_2D_SRC_WND_HEIGHT0 0x1e8
00344 #define REG_2D_SRC_WND_HEIGHT1 0x1e9
00345 #define REG_2D_DEST_WND_WIDTH0 0x1ec
00346 #define REG_2D_DEST_WND_WIDTH1 0x1ed
00347 #define REG_2D_DEST_WND_HEIGHT0 0x1f0
00348 #define REG_2D_DEST_WND_HEIGHT1 0x1f1
00349 #define REG_2D_DEST_WND_START_ADDR0 0x1f4
00350 #define REG_2D_DEST_WND_START_ADDR1 0x1f5
00351 #define REG_2D_DEST_WND_START_ADDR2 0x1f6
00352 #define REG_2D_DEST_WND_ADDR_OFFSET0 0x1f8
00353 #define REG_2D_DEST_WND_ADDR_OFFSET1 0x1f9
00354 #define REG_2D_WRITE_PATTERN0 0x1fc
00355 #define REG_2D_WRITE_PATTERN1 0x1fd
00356 #define REG_2D_WRITE_PATTERN2 0x1fe
00357 #define REG_2D_BRUSH_WND_START_ADDR0 0x204
00358 #define REG_2D_BRUSH_WND_START_ADDR1 0x205
00359 #define REG_2D_BRUSH_WND_START_ADDR2 0x206
00360 #define REG_2D_BRUSH_WND_ADDR_OFFSET0 0x208
00361 #define REG_2D_BRUSH_WND_ADDR_OFFSET1 0x209
00362 #define REG_2D_BRUSH_WND_WIDTH0 0x214
00363 #define REG_2D_BRUSH_WND_WIDTH1 0x215
00364 #define REG_2D_BRUSH_WND_HEIGHT0 0x218
00365 #define REG_2D_BRUSH_WND_HEIGHT1 0x219
00366 #define REG_2D_CMD_FIFO_INT_EN 0x21c
00367 #define REG_2D_CMD_FIFO_INT_STATUS 0x21e
00368 #define REG_2D_CMD_FIFO_FLAG 0x220
00369 #define REG_2D_CMD_FIFO_IND 0x222
00370
00371
00372
00373 #define REG_I2C_DATA_OUT 0x230
00374 #define REG_I2C_CTL 0x231
00375 #define REG_I2C_EN_OUT 0x232
00376 #define REG_I2C_BAUD 0x233
00377 #define REG_I2C_STATUS 0x234
00378 #define REG_I2C_INTERRUPT 0x235
00379 #define REG_I2C_DATA_READY 0x236
00380 #define REG_I2C_DATA_IN 0x237
00381
00382
00383 #define REG_Sub_mode 0x250
00384 #define REG_Sub_CLK_Divide 0x252
00385 #define REG_Sub_Hori_Size 0x254
00386 #define REG_Sub_Vert_Size 0x25c
00387 #define REG_Sub_Type 0x260
00388 #define REG_Sub_Bpp 0x261
00389 #define REG_Sub_TFT_Start 0x262
00390 #define REG_Sub_SCLK_Divide 0x263
00391
00392
00393 #define REG_Sub_Ctl_0 0x270
00394 #define REG_Sub_Ctl_1 0x271
00395 #define REG_Sub_YVU 0x268
00396 #define REG_Sub_Y_Offset 0x269
00397 #define REG_Sub_Cb_Offset 0x26a
00398 #define REG_Sub_Cr_Offset 0x26b
00399 #define REG_Sub_Data_0 0x26c
00400 #define REG_Sub_Data_1 0x26d
00401 #define REG_Sub_RS 0x26e
00402 #define REG_Sub_Start_Adr_0 0x274
00403 #define REG_Sub_Start_Adr_1 0x275
00404 #define REG_Sub_Start_Adr_2 0x276
00405 #define REG_Sub_Offset_0 0x278
00406 #define REG_Sub_Offset_1 0x279
00407 #define REG_Sub_Ready 0x27d
00408
00409 #define REG_LCD0_Rise_0 0x2b0
00410 #define REG_LCD0_Rise_1 0x2b1
00411 #define REG_LCD0_Fall_0 0x2b4
00412 #define REG_LCD0_Fall_1 0x2b5
00413 #define REG_LCD0_Period_0 0x2b8
00414 #define REG_LCD0_Period_1 0x2b9
00415 #define REG_LCD0_Ctl_0 0x2bc
00416 #define REG_LCD0_Ctl_1 0x2bd
00417 #define REG_LCD1_Rise_0 0x2c0
00418 #define REG_LCD1_Rise_1 0x2c1
00419 #define REG_LCD1_Fall_0 0x2c4
00420 #define REG_LCD1_Fall_1 0x2c5
00421 #define REG_LCD1_Period_0 0x2c8
00422 #define REG_LCD1_Period_1 0x2c9
00423 #define REG_LCD1_Ctl_0 0x2cc
00424 #define REG_LCD1_Ctl_1 0x2cd
00425 #define REG_LCD2_Rise_0 0x2d0
00426 #define REG_LCD2_Rise_1 0x2d1
00427 #define REG_LCD2_Fall_0 0x2d4
00428 #define REG_LCD2_Fall_1 0x2d5
00429 #define REG_LCD2_Period_0 0x2d8
00430 #define REG_LCD2_Period_1 0x2d9
00431 #define REG_LCD2_Ctl_0 0x2dc
00432 #define REG_LCD2_Ctl_1 0x2dd
00433 #define REG_LCD3_Rise_0 0x2e0
00434 #define REG_LCD3_Rise_1 0x2e1
00435 #define REG_LCD3_Fall_0 0x2e4
00436 #define REG_LCD3_Fall_1 0x2e5
00437 #define REG_LCD3_Period_0 0x2e8
00438 #define REG_LCD3_Period_1 0x2e9
00439 #define REG_LCD3_Ctl_0 0x2ec
00440 #define REG_LCD3_Ctl_1 0x2ed
00441 #define REG_LCD4_Rise_0 0x2f0
00442 #define REG_LCD4_Rise_1 0x2f1
00443 #define REG_LCD4_Fall_0 0x2f4
00444 #define REG_LCD4_Fall_1 0x2f5
00445 #define REG_LCD4_Period_0 0x2f8
00446 #define REG_LCD4_Period_1 0x2f9
00447 #define REG_LCD4_Ctl_0 0x2fc
00448 #define REG_LCD4_Ctl_1 0x2fd
00449 #define REG_LCD5_Rise_0 0x300
00450 #define REG_LCD5_Rise_1 0x301
00451 #define REG_LCD5_Fall_0 0x304
00452 #define REG_LCD5_Fall_1 0x305
00453 #define REG_LCD5_Period_0 0x308
00454 #define REG_LCD5_Period_1 0x309
00455 #define REG_LCD5_Ctl_0 0x30c
00456 #define REG_LCD5_Ctl_1 0x30d
00457 #define REG_LCD6_Rise_0 0x310
00458 #define REG_LCD6_Rise_1 0x311
00459 #define REG_LCD6_Fall_0 0x314
00460 #define REG_LCD6_Fall_1 0x315
00461 #define REG_LCD6_Period_0 0x318
00462 #define REG_LCD6_Period_1 0x319
00463 #define REG_LCD6_Ctl_0 0x31c
00464 #define REG_LCD6_Ctl_1 0x31d
00465 #define REG_LCD7_Rise_0 0x320
00466 #define REG_LCD7_Rise_1 0x321
00467 #define REG_LCD7_Fall_0 0x324
00468 #define REG_LCD7_Fall_1 0x325
00469 #define REG_LCD7_Period_0 0x328
00470 #define REG_LCD7_Period_1 0x329
00471 #define REG_LCD7_Ctl_0 0x32c
00472 #define REG_LCD7_Ctl_1 0x32d
00473
00474
00475 #define REG_FRC_FRAME_CTL 0x334
00476 #define REG_FRC_ENABLE 0x336
00477
00478 #define REG_JPEG_RESIZER_CTL 0x360
00479 #define REG_JPEG_RESIZER_STARTX_0 0x364
00480 #define REG_JPEG_RESIZER_STARTX_1 0x365
00481 #define REG_JPEG_RESIZER_STARTY_0 0x366
00482 #define REG_JPEG_RESIZER_STARTY_1 0x367
00483 #define REG_JPEG_RESIZER_ENDX_0 0x368
00484 #define REG_JPEG_RESIZER_ENDX_1 0x369
00485 #define REG_JPEG_RESIZER_ENDY_0 0x36a
00486 #define REG_JPEG_RESIZER_ENDY_1 0x36b
00487 #define REG_JPEG_RESIZER_OP_0 0x36c
00488 #define REG_JPEG_RESIZER_OP_1 0x36e
00489
00490
00491
00492 #define REG_JPEG_CTRL 0x380
00493 #define REG_JPEG_STATUS 0x382
00494 #define REG_JPEG_STATUS1 0x383
00495
00496 #define REG_JPEG_RAW_STATUS 0x384
00497 #define REG_JPEG_RAW_STATUS1 0x385
00498
00499 #define REG_JPEG_INTR_CTL0 0x386
00500 #define REG_JPEG_INTR_CTL1 0x387
00501
00502 #define REG_JPEG_START_STOP 0x38a
00503
00504 #define REG_JPEG_FIFO_CTL 0x3a0
00505 #define REG_JPEG_FIFO_STATUS 0x3a2
00506 #define REG_JPEG_FIFO_SIZE 0x3a4
00507
00508
00509 #define REG_JPEG_ENCODE_SIZE_LIMIT_0 0x3B0
00510 #define REG_JPEG_ENCODE_SIZE_LIMIT_1 0x3B1
00511 #define REG_JPEG_ENCODE_SIZE_LIMIT_2 0x3B2
00512
00513 #define REG_JPEG_ENCODE_SIZE_RESULT_0 0x3b4
00514 #define REG_JPEG_ENCODE_SIZE_RESULT_1 0x3b5
00515 #define REG_JPEG_ENCODE_SIZE_RESULT_2 0x3b6
00516
00517 #define REG_JPEG_FILE_SIZE_0 0x3B8
00518 #define REG_JPEG_FILE_SIZE_1 0x3B9
00519 #define REG_JPEG_FILE_SIZE_2 0x3BA
00520
00521 #define REG_JPEG_DECODE_X_SIZE 0x3d8
00522 #define REG_JPEG_DECODE_Y_SIZE 0x3dc
00523
00524 #define REG_JPEG_OP_MODE_ENC 0x400
00525 #define REG_JPEG_OP_MODE 0x401
00526
00527 #define REG_JPEG_CMD 0x402
00528
00529 #define REG_DRI_SETTING 0x40a
00530
00531 #define REG_JPEG_DECODE_VALUE 0x404
00532
00533 #define REG_JPEG_Y_PIXEL_SIZE_0 0x40c
00534 #define REG_JPEG_Y_PIXEL_SIZE_1 0x40d
00535 #define REG_JPEG_X_PIXEL_SIZE_0 0x40e
00536 #define REG_JPEG_X_PIXEL_SIZE_1 0x40f
00537
00538 #define REG_JPEG_SRC_START_ADDR_0 0x410
00539 #define REG_JPEG_SRC_START_ADDR_1 0x411
00540 #define REG_JPEG_SRC_START_ADDR_2 0x412
00541 #define REG_JPEG_SRC_START_ADDR_3 0x413
00542
00543 #define REG_JPEG_DEST_START_ADDR_0 0x414
00544 #define REG_JPEG_DEST_START_ADDR_1 0x415
00545 #define REG_JPEG_DEST_START_ADDR_2 0x416
00546 #define REG_JPEG_DEST_START_ADDR_3 0x417
00547
00548 #define REG_JPEG_RST_MARKER 0x41c
00549
00550 #define REG_JPEG_RST_MARKER_STATUS 0x41e
00551
00552 #define REG_JPEG_INSERT_MARKER00 0x420
00553 #define REG_JPEG_INSERT_MARKER01 0x422
00554 #define REG_JPEG_MARKER_LENGTH00 0x424
00555 #define REG_JPEG_MARKER_LENGTH01 0x426
00556
00557 #define REG_JPEG_MARKER_DATA_00 0x428
00558 #define REG_JPEG_MARKER_DATA_01 0x42a
00559 #define REG_JPEG_MARKER_DATA_02 0x42c
00560 #define REG_JPEG_MARKER_DATA_03 0x42e
00561 #define REG_JPEG_MARKER_DATA_04 0x430
00562 #define REG_JPEG_MARKER_DATA_05 0x432
00563 #define REG_JPEG_MARKER_DATA_06 0x434
00564 #define REG_JPEG_MARKER_DATA_07 0x436
00565 #define REG_JPEG_MARKER_DATA_08 0x438
00566 #define REG_JPEG_MARKER_DATA_09 0x43a
00567 #define REG_JPEG_MARKER_DATA_10 0x43c
00568 #define REG_JPEG_MARKER_DATA_11 0x43e
00569 #define REG_JPEG_MARKER_DATA_12 0x440
00570 #define REG_JPEG_MARKER_DATA_13 0x442
00571 #define REG_JPEG_MARKER_DATA_14 0x444
00572 #define REG_JPEG_MARKER_DATA_15 0x446
00573 #define REG_JPEG_MARKER_DATA_16 0x448
00574 #define REG_JPEG_MARKER_DATA_17 0x44a
00575 #define REG_JPEG_MARKER_DATA_18 0x44c
00576 #define REG_JPEG_MARKER_DATA_19 0x44e
00577 #define REG_JPEG_MARKER_DATA_20 0x450
00578 #define REG_JPEG_MARKER_DATA_21 0x452
00579 #define REG_JPEG_MARKER_DATA_22 0x454
00580 #define REG_JPEG_MARKER_DATA_23 0x456
00581 #define REG_JPEG_MARKER_DATA_24 0x458
00582 #define REG_JPEG_MARKER_DATA_25 0x45a
00583 #define REG_JPEG_MARKER_DATA_26 0x45c
00584 #define REG_JPEG_MARKER_DATA_27 0x45e
00585 #define REG_JPEG_MARKER_DATA_28 0x460
00586 #define REG_JPEG_MARKER_DATA_29 0x462
00587 #define REG_JPEG_MARKER_DATA_30 0x464
00588 #define REG_JPEG_MARKER_DATA_31 0x466
00589
00590 #define REG_JPEG_SOI_CONST_00 0x468
00591 #define REG_JPEG_SOI_CONST_01 0x46a
00592
00593 #define REG_JPEG_JFIF_CONST_00 0x46c
00594 #define REG_JPEG_JFIF_CONST_01 0x46e
00595 #define REG_JPEG_JFIF_CONST_02 0x470
00596 #define REG_JPEG_JFIF_CONST_03 0x472
00597 #define REG_JPEG_JFIF_CONST_04 0x474
00598 #define REG_JPEG_JFIF_CONST_05 0x476
00599 #define REG_JPEG_JFIF_CONST_06 0x478
00600 #define REG_JPEG_JFIF_CONST_07 0x47a
00601 #define REG_JPEG_JFIF_CONST_08 0x47c
00602 #define REG_JPEG_JFIF_CONST_09 0x47e
00603 #define REG_JPEG_JFIF_CONST_10 0x480
00604 #define REG_JPEG_JFIF_CONST_11 0x482
00605 #define REG_JPEG_JFIF_CONST_12 0x484
00606 #define REG_JPEG_JFIF_CONST_13 0x486
00607 #define REG_JPEG_JFIF_CONST_14 0x488
00608 #define REG_JPEG_JFIF_CONST_15 0x48a
00609 #define REG_JPEG_JFIF_CONST_16 0x48c
00610 #define REG_JPEG_JFIF_CONST_17 0x48e
00611
00612 #define REG_JPEG_LUM_DC_HT_CONST_00 0x490
00613 #define REG_JPEG_LUM_DC_HT_CONST_01 0x492
00614 #define REG_JPEG_LUM_DC_HT_CONST_02 0x494
00615 #define REG_JPEG_LUM_DC_HT_CONST_03 0x496
00616 #define REG_JPEG_LUM_DC_HT_CONST_04 0x498
00617
00618 #define REG_JPEG_CHR_DC_HT_CONST_00 0x4a0
00619 #define REG_JPEG_CHR_DC_HT_CONST_01 0x4a2
00620 #define REG_JPEG_CHR_DC_HT_CONST_02 0x4a4
00621 #define REG_JPEG_CHR_DC_HT_CONST_03 0x4a6
00622 #define REG_JPEG_CHR_DC_HT_CONST_04 0x4a8
00623
00624 #define REG_JPEG_LUM_AC_HT_CONST_00 0x4b0
00625 #define REG_JPEG_LUM_AC_HT_CONST_01 0x4b2
00626 #define REG_JPEG_LUM_AC_HT_CONST_02 0x4b4
00627 #define REG_JPEG_LUM_AC_HT_CONST_03 0x4b6
00628 #define REG_JPEG_LUM_AC_HT_CONST_04 0x4b8
00629
00630 #define REG_JPEG_CHR_AC_HT_CONST_00 0x4c0
00631 #define REG_JPEG_CHR_AC_HT_CONST_01 0x4c2
00632 #define REG_JPEG_CHR_AC_HT_CONST_02 0x4c4
00633 #define REG_JPEG_CHR_AC_HT_CONST_03 0x4c6
00634 #define REG_JPEG_CHR_AC_HT_CONST_04 0x4c8
00635
00636 #define REG_JPEG_LUM_QT_CONST_00 0x4d0
00637 #define REG_JPEG_LUM_QT_CONST_01 0x4d2
00638 #define REG_JPEG_LUM_QT_CONST_02 0x4d4
00639 #define REG_JPEG_LUM_QT_CONST_03 0x4d6
00640 #define REG_JPEG_LUM_QT_CONST_04 0x4d8
00641
00642 #define REG_JPEG_CHR_QT_CONST_00 0x4e0
00643 #define REG_JPEG_CHR_QT_CONST_01 0x4e2
00644 #define REG_JPEG_CHR_QT_CONST_02 0x4e4
00645 #define REG_JPEG_CHR_QT_CONST_03 0x4e6
00646 #define REG_JPEG_CHR_QT_CONST_04 0x4e8
00647
00648 #define REG_JPEG_SOF_CONST_00 0x4f0
00649 #define REG_JPEG_SOF_CONST_01 0x4f2
00650 #define REG_JPEG_SOF_CONST_02 0x4f4
00651 #define REG_JPEG_SOF_CONST_03 0x4f6
00652 #define REG_JPEG_SOF_CONST_04 0x4f8
00653
00654 #define REG_JPEG_QUANT_T0_00 0x500
00655 #define REG_JPEG_QUANT_T0_01 0x502
00656 #define REG_JPEG_QUANT_T0_02 0x504
00657 #define REG_JPEG_QUANT_T0_03 0x506
00658 #define REG_JPEG_QUANT_T0_04 0x508
00659 #define REG_JPEG_QUANT_T0_05 0x50a
00660 #define REG_JPEG_QUANT_T0_06 0x50c
00661 #define REG_JPEG_QUANT_T0_07 0x50e
00662 #define REG_JPEG_QUANT_T0_08 0x510
00663 #define REG_JPEG_QUANT_T0_09 0x512
00664 #define REG_JPEG_QUANT_T0_10 0x514
00665 #define REG_JPEG_QUANT_T0_11 0x516
00666 #define REG_JPEG_QUANT_T0_12 0x518
00667 #define REG_JPEG_QUANT_T0_13 0x51a
00668 #define REG_JPEG_QUANT_T0_14 0x51c
00669 #define REG_JPEG_QUANT_T0_15 0x51e
00670 #define REG_JPEG_QUANT_T0_16 0x520
00671 #define REG_JPEG_QUANT_T0_17 0x522
00672 #define REG_JPEG_QUANT_T0_18 0x524
00673 #define REG_JPEG_QUANT_T0_19 0x526
00674 #define REG_JPEG_QUANT_T0_20 0x528
00675 #define REG_JPEG_QUANT_T0_21 0x52a
00676 #define REG_JPEG_QUANT_T0_22 0x52c
00677 #define REG_JPEG_QUANT_T0_23 0x52e
00678 #define REG_JPEG_QUANT_T0_24 0x530
00679 #define REG_JPEG_QUANT_T0_25 0x532
00680 #define REG_JPEG_QUANT_T0_26 0x534
00681 #define REG_JPEG_QUANT_T0_27 0x536
00682 #define REG_JPEG_QUANT_T0_28 0x538
00683 #define REG_JPEG_QUANT_T0_29 0x53a
00684 #define REG_JPEG_QUANT_T0_30 0x53c
00685 #define REG_JPEG_QUANT_T0_31 0x53e
00686 #define REG_JPEG_QUANT_T0_32 0x540
00687 #define REG_JPEG_QUANT_T0_33 0x542
00688 #define REG_JPEG_QUANT_T0_34 0x544
00689 #define REG_JPEG_QUANT_T0_35 0x546
00690 #define REG_JPEG_QUANT_T0_36 0x548
00691 #define REG_JPEG_QUANT_T0_37 0x54a
00692 #define REG_JPEG_QUANT_T0_38 0x54c
00693 #define REG_JPEG_QUANT_T0_39 0x54e
00694 #define REG_JPEG_QUANT_T0_40 0x550
00695 #define REG_JPEG_QUANT_T0_41 0x552
00696 #define REG_JPEG_QUANT_T0_42 0x554
00697 #define REG_JPEG_QUANT_T0_43 0x556
00698 #define REG_JPEG_QUANT_T0_44 0x558
00699 #define REG_JPEG_QUANT_T0_45 0x55a
00700 #define REG_JPEG_QUANT_T0_46 0x55c
00701 #define REG_JPEG_QUANT_T0_47 0x55e
00702 #define REG_JPEG_QUANT_T0_48 0x560
00703 #define REG_JPEG_QUANT_T0_49 0x562
00704 #define REG_JPEG_QUANT_T0_50 0x564
00705 #define REG_JPEG_QUANT_T0_51 0x566
00706 #define REG_JPEG_QUANT_T0_52 0x568
00707 #define REG_JPEG_QUANT_T0_53 0x56a
00708 #define REG_JPEG_QUANT_T0_54 0x56c
00709 #define REG_JPEG_QUANT_T0_55 0x56e
00710 #define REG_JPEG_QUANT_T0_56 0x570
00711 #define REG_JPEG_QUANT_T0_57 0x572
00712 #define REG_JPEG_QUANT_T0_58 0x574
00713 #define REG_JPEG_QUANT_T0_59 0x576
00714 #define REG_JPEG_QUANT_T0_60 0x578
00715 #define REG_JPEG_QUANT_T0_61 0x57a
00716 #define REG_JPEG_QUANT_T0_62 0x57c
00717 #define REG_JPEG_QUANT_T0_63 0x57e
00718
00719 #define REG_JPEG_QUANT_T1_00 0x580
00720 #define REG_JPEG_QUANT_T1_01 0x582
00721 #define REG_JPEG_QUANT_T1_02 0x584
00722 #define REG_JPEG_QUANT_T1_03 0x586
00723 #define REG_JPEG_QUANT_T1_04 0x588
00724 #define REG_JPEG_QUANT_T1_05 0x58a
00725 #define REG_JPEG_QUANT_T1_06 0x58c
00726 #define REG_JPEG_QUANT_T1_07 0x58e
00727 #define REG_JPEG_QUANT_T1_08 0x590
00728 #define REG_JPEG_QUANT_T1_09 0x592
00729 #define REG_JPEG_QUANT_T1_10 0x594
00730 #define REG_JPEG_QUANT_T1_11 0x596
00731 #define REG_JPEG_QUANT_T1_12 0x598
00732 #define REG_JPEG_QUANT_T1_13 0x59a
00733 #define REG_JPEG_QUANT_T1_14 0x59c
00734 #define REG_JPEG_QUANT_T1_15 0x59e
00735 #define REG_JPEG_QUANT_T1_16 0x5a0
00736 #define REG_JPEG_QUANT_T1_17 0x5a2
00737 #define REG_JPEG_QUANT_T1_18 0x5a4
00738 #define REG_JPEG_QUANT_T1_19 0x5a6
00739 #define REG_JPEG_QUANT_T1_20 0x5a8
00740 #define REG_JPEG_QUANT_T1_21 0x5aa
00741 #define REG_JPEG_QUANT_T1_22 0x5ac
00742 #define REG_JPEG_QUANT_T1_23 0x5ae
00743 #define REG_JPEG_QUANT_T1_24 0x5b0
00744 #define REG_JPEG_QUANT_T1_25 0x5b2
00745 #define REG_JPEG_QUANT_T1_26 0x5b4
00746 #define REG_JPEG_QUANT_T1_27 0x5b6
00747 #define REG_JPEG_QUANT_T1_28 0x5b8
00748 #define REG_JPEG_QUANT_T1_29 0x5ba
00749 #define REG_JPEG_QUANT_T1_30 0x5bc
00750 #define REG_JPEG_QUANT_T1_31 0x5be
00751 #define REG_JPEG_QUANT_T1_32 0x5c0
00752 #define REG_JPEG_QUANT_T1_33 0x5c2
00753 #define REG_JPEG_QUANT_T1_34 0x5c4
00754 #define REG_JPEG_QUANT_T1_35 0x5c6
00755 #define REG_JPEG_QUANT_T1_36 0x5c8
00756 #define REG_JPEG_QUANT_T1_37 0x5ca
00757 #define REG_JPEG_QUANT_T1_38 0x5cc
00758 #define REG_JPEG_QUANT_T1_39 0x5ce
00759 #define REG_JPEG_QUANT_T1_40 0x5d0
00760 #define REG_JPEG_QUANT_T1_41 0x5d2
00761 #define REG_JPEG_QUANT_T1_42 0x5d4
00762 #define REG_JPEG_QUANT_T1_43 0x5d6
00763 #define REG_JPEG_QUANT_T1_44 0x5d8
00764 #define REG_JPEG_QUANT_T1_45 0x5da
00765 #define REG_JPEG_QUANT_T1_46 0x5dc
00766 #define REG_JPEG_QUANT_T1_47 0x5de
00767 #define REG_JPEG_QUANT_T1_48 0x5e0
00768 #define REG_JPEG_QUANT_T1_49 0x5e2
00769 #define REG_JPEG_QUANT_T1_50 0x5e4
00770 #define REG_JPEG_QUANT_T1_51 0x5e6
00771 #define REG_JPEG_QUANT_T1_52 0x5e8
00772 #define REG_JPEG_QUANT_T1_53 0x5ea
00773 #define REG_JPEG_QUANT_T1_54 0x5ec
00774 #define REG_JPEG_QUANT_T1_55 0x5ee
00775 #define REG_JPEG_QUANT_T1_56 0x5f0
00776 #define REG_JPEG_QUANT_T1_57 0x5f2
00777 #define REG_JPEG_QUANT_T1_58 0x5f4
00778 #define REG_JPEG_QUANT_T1_59 0x5f6
00779 #define REG_JPEG_QUANT_T1_60 0x5f8
00780 #define REG_JPEG_QUANT_T1_61 0x5fa
00781 #define REG_JPEG_QUANT_T1_62 0x5fc
00782 #define REG_JPEG_QUANT_T1_63 0x5fe
00783
00784 #define REG_JPEG_DC_T0_R0_00 0x600
00785 #define REG_JPEG_DC_T0_R0_01 0x602
00786 #define REG_JPEG_DC_T0_R0_02 0x604
00787 #define REG_JPEG_DC_T0_R0_03 0x606
00788 #define REG_JPEG_DC_T0_R0_04 0x608
00789 #define REG_JPEG_DC_T0_R0_05 0x60a
00790 #define REG_JPEG_DC_T0_R0_06 0x60c
00791 #define REG_JPEG_DC_T0_R0_07 0x60e
00792 #define REG_JPEG_DC_T0_R0_08 0x610
00793 #define REG_JPEG_DC_T0_R0_09 0x612
00794 #define REG_JPEG_DC_T0_R0_10 0x614
00795 #define REG_JPEG_DC_T0_R0_11 0x616
00796 #define REG_JPEG_DC_T0_R0_12 0x618
00797 #define REG_JPEG_DC_T0_R0_13 0x61a
00798 #define REG_JPEG_DC_T0_R0_14 0x61c
00799 #define REG_JPEG_DC_T0_R0_15 0x61e
00800
00801 #define REG_JPEG_DC_T0_R1_00 0x620
00802 #define REG_JPEG_DC_T0_R1_01 0x622
00803 #define REG_JPEG_DC_T0_R1_02 0x624
00804 #define REG_JPEG_DC_T0_R1_03 0x626
00805 #define REG_JPEG_DC_T0_R1_04 0x628
00806 #define REG_JPEG_DC_T0_R1_05 0x62a
00807 #define REG_JPEG_DC_T0_R1_06 0x62c
00808 #define REG_JPEG_DC_T0_R1_07 0x62e
00809 #define REG_JPEG_DC_T0_R1_08 0x630
00810 #define REG_JPEG_DC_T0_R1_09 0x632
00811 #define REG_JPEG_DC_T0_R1_10 0x634
00812 #define REG_JPEG_DC_T0_R1_11 0x636
00813
00814 #define REG_JPEG_AC_T0_R0_00 0x640
00815 #define REG_JPEG_AC_T0_R0_01 0x642
00816 #define REG_JPEG_AC_T0_R0_02 0x644
00817 #define REG_JPEG_AC_T0_R0_03 0x646
00818 #define REG_JPEG_AC_T0_R0_04 0x648
00819 #define REG_JPEG_AC_T0_R0_05 0x64a
00820 #define REG_JPEG_AC_T0_R0_06 0x64c
00821 #define REG_JPEG_AC_T0_R0_07 0x64e
00822 #define REG_JPEG_AC_T0_R0_08 0x650
00823 #define REG_JPEG_AC_T0_R0_09 0x652
00824 #define REG_JPEG_AC_T0_R0_10 0x654
00825 #define REG_JPEG_AC_T0_R0_11 0x656
00826 #define REG_JPEG_AC_T0_R0_12 0x658
00827 #define REG_JPEG_AC_T0_R0_13 0x65a
00828 #define REG_JPEG_AC_T0_R0_14 0x65c
00829 #define REG_JPEG_AC_T0_R0_15 0x65e
00830
00831 #define REG_JPEG_AC_T0_R1_00 0x660
00832 #define REG_JPEG_AC_T0_R1_01 0x662
00833 #define REG_JPEG_AC_T0_R1_02 0x664
00834 #define REG_JPEG_AC_T0_R1_03 0x666
00835 #define REG_JPEG_AC_T0_R1_04 0x668
00836 #define REG_JPEG_AC_T0_R1_05 0x66a
00837 #define REG_JPEG_AC_T0_R1_06 0x66c
00838 #define REG_JPEG_AC_T0_R1_07 0x66e
00839 #define REG_JPEG_AC_T0_R1_08 0x670
00840 #define REG_JPEG_AC_T0_R1_09 0x672
00841 #define REG_JPEG_AC_T0_R1_10 0x674
00842 #define REG_JPEG_AC_T0_R1_11 0x676
00843 #define REG_JPEG_AC_T0_R1_12 0x678
00844 #define REG_JPEG_AC_T0_R1_13 0x67a
00845 #define REG_JPEG_AC_T0_R1_14 0x67c
00846 #define REG_JPEG_AC_T0_R1_15 0x67e
00847 #define REG_JPEG_AC_T0_R1_16 0x680
00848 #define REG_JPEG_AC_T0_R1_17 0x682
00849 #define REG_JPEG_AC_T0_R1_18 0x684
00850 #define REG_JPEG_AC_T0_R1_19 0x686
00851 #define REG_JPEG_AC_T0_R1_20 0x688
00852 #define REG_JPEG_AC_T0_R1_21 0x68a
00853 #define REG_JPEG_AC_T0_R1_22 0x68c
00854 #define REG_JPEG_AC_T0_R1_23 0x68e
00855 #define REG_JPEG_AC_T0_R1_24 0x690
00856 #define REG_JPEG_AC_T0_R1_25 0x692
00857 #define REG_JPEG_AC_T0_R1_26 0x694
00858 #define REG_JPEG_AC_T0_R1_27 0x696
00859 #define REG_JPEG_AC_T0_R1_28 0x698
00860 #define REG_JPEG_AC_T0_R1_29 0x69a
00861 #define REG_JPEG_AC_T0_R1_30 0x69c
00862 #define REG_JPEG_AC_T0_R1_31 0x69e
00863 #define REG_JPEG_AC_T0_R1_32 0x6a0
00864 #define REG_JPEG_AC_T0_R1_33 0x6a2
00865 #define REG_JPEG_AC_T0_R1_34 0x6a4
00866 #define REG_JPEG_AC_T0_R1_35 0x6a6
00867 #define REG_JPEG_AC_T0_R1_36 0x6a8
00868 #define REG_JPEG_AC_T0_R1_37 0x6aa
00869 #define REG_JPEG_AC_T0_R1_38 0x6ac
00870 #define REG_JPEG_AC_T0_R1_39 0x6ae
00871 #define REG_JPEG_AC_T0_R1_40 0x6b0
00872 #define REG_JPEG_AC_T0_R1_41 0x6b2
00873 #define REG_JPEG_AC_T0_R1_42 0x6b4
00874 #define REG_JPEG_AC_T0_R1_43 0x6b6
00875 #define REG_JPEG_AC_T0_R1_44 0x6b8
00876 #define REG_JPEG_AC_T0_R1_45 0x6ba
00877 #define REG_JPEG_AC_T0_R1_46 0x6bc
00878 #define REG_JPEG_AC_T0_R1_47 0x6be
00879 #define REG_JPEG_AC_T0_R1_48 0x6c0
00880 #define REG_JPEG_AC_T0_R1_49 0x6c2
00881 #define REG_JPEG_AC_T0_R1_50 0x6c4
00882 #define REG_JPEG_AC_T0_R1_51 0x6c6
00883 #define REG_JPEG_AC_T0_R1_52 0x6c8
00884 #define REG_JPEG_AC_T0_R1_53 0x6ca
00885 #define REG_JPEG_AC_T0_R1_54 0x6cc
00886 #define REG_JPEG_AC_T0_R1_55 0x6ce
00887 #define REG_JPEG_AC_T0_R1_56 0x6d0
00888 #define REG_JPEG_AC_T0_R1_57 0x6d2
00889 #define REG_JPEG_AC_T0_R1_58 0x6d4
00890 #define REG_JPEG_AC_T0_R1_59 0x6d6
00891 #define REG_JPEG_AC_T0_R1_60 0x6d8
00892 #define REG_JPEG_AC_T0_R1_61 0x6da
00893 #define REG_JPEG_AC_T0_R1_62 0x6dc
00894 #define REG_JPEG_AC_T0_R1_63 0x6de
00895 #define REG_JPEG_AC_T0_R1_64 0x6e0
00896 #define REG_JPEG_AC_T0_R1_65 0x6e2
00897 #define REG_JPEG_AC_T0_R1_66 0x6e4
00898 #define REG_JPEG_AC_T0_R1_67 0x6e6
00899 #define REG_JPEG_AC_T0_R1_68 0x6e8
00900 #define REG_JPEG_AC_T0_R1_69 0x6ea
00901 #define REG_JPEG_AC_T0_R1_70 0x6ec
00902 #define REG_JPEG_AC_T0_R1_71 0x6ee
00903 #define REG_JPEG_AC_T0_R1_72 0x6f0
00904 #define REG_JPEG_AC_T0_R1_73 0x6f2
00905 #define REG_JPEG_AC_T0_R1_74 0x6f4
00906 #define REG_JPEG_AC_T0_R1_75 0x6f6
00907 #define REG_JPEG_AC_T0_R1_76 0x6f8
00908 #define REG_JPEG_AC_T0_R1_77 0x6fa
00909 #define REG_JPEG_AC_T0_R1_78 0x6fc
00910 #define REG_JPEG_AC_T0_R1_79 0x6fe
00911 #define REG_JPEG_AC_T0_R1_80 0x700
00912 #define REG_JPEG_AC_T0_R1_81 0x702
00913 #define REG_JPEG_AC_T0_R1_82 0x704
00914 #define REG_JPEG_AC_T0_R1_83 0x706
00915 #define REG_JPEG_AC_T0_R1_84 0x708
00916 #define REG_JPEG_AC_T0_R1_85 0x70a
00917 #define REG_JPEG_AC_T0_R1_86 0x70c
00918 #define REG_JPEG_AC_T0_R1_87 0x70e
00919 #define REG_JPEG_AC_T0_R1_88 0x710
00920 #define REG_JPEG_AC_T0_R1_89 0x712
00921 #define REG_JPEG_AC_T0_R1_90 0x714
00922 #define REG_JPEG_AC_T0_R1_91 0x716
00923 #define REG_JPEG_AC_T0_R1_92 0x718
00924 #define REG_JPEG_AC_T0_R1_93 0x71a
00925 #define REG_JPEG_AC_T0_R1_94 0x71c
00926 #define REG_JPEG_AC_T0_R1_95 0x71e
00927 #define REG_JPEG_AC_T0_R1_96 0x720
00928 #define REG_JPEG_AC_T0_R1_97 0x722
00929 #define REG_JPEG_AC_T0_R1_98 0x724
00930 #define REG_JPEG_AC_T0_R1_99 0x726
00931 #define REG_JPEG_AC_T0_R1_100 0x728
00932 #define REG_JPEG_AC_T0_R1_101 0x72a
00933 #define REG_JPEG_AC_T0_R1_102 0x72c
00934 #define REG_JPEG_AC_T0_R1_103 0x72e
00935 #define REG_JPEG_AC_T0_R1_104 0x730
00936 #define REG_JPEG_AC_T0_R1_105 0x732
00937 #define REG_JPEG_AC_T0_R1_106 0x734
00938 #define REG_JPEG_AC_T0_R1_107 0x736
00939 #define REG_JPEG_AC_T0_R1_108 0x738
00940 #define REG_JPEG_AC_T0_R1_109 0x73a
00941 #define REG_JPEG_AC_T0_R1_110 0x73c
00942 #define REG_JPEG_AC_T0_R1_111 0x73e
00943 #define REG_JPEG_AC_T0_R1_112 0x740
00944 #define REG_JPEG_AC_T0_R1_113 0x742
00945 #define REG_JPEG_AC_T0_R1_114 0x744
00946 #define REG_JPEG_AC_T0_R1_115 0x746
00947 #define REG_JPEG_AC_T0_R1_116 0x748
00948 #define REG_JPEG_AC_T0_R1_117 0x74a
00949 #define REG_JPEG_AC_T0_R1_118 0x74c
00950 #define REG_JPEG_AC_T0_R1_119 0x74e
00951 #define REG_JPEG_AC_T0_R1_120 0x750
00952 #define REG_JPEG_AC_T0_R1_121 0x752
00953 #define REG_JPEG_AC_T0_R1_122 0x754
00954 #define REG_JPEG_AC_T0_R1_123 0x756
00955 #define REG_JPEG_AC_T0_R1_124 0x758
00956 #define REG_JPEG_AC_T0_R1_125 0x75a
00957 #define REG_JPEG_AC_T0_R1_126 0x75c
00958 #define REG_JPEG_AC_T0_R1_127 0x75e
00959 #define REG_JPEG_AC_T0_R1_128 0x760
00960 #define REG_JPEG_AC_T0_R1_129 0x762
00961 #define REG_JPEG_AC_T0_R1_130 0x764
00962 #define REG_JPEG_AC_T0_R1_131 0x766
00963 #define REG_JPEG_AC_T0_R1_132 0x768
00964 #define REG_JPEG_AC_T0_R1_133 0x76a
00965 #define REG_JPEG_AC_T0_R1_134 0x76c
00966 #define REG_JPEG_AC_T0_R1_135 0x76e
00967 #define REG_JPEG_AC_T0_R1_136 0x770
00968 #define REG_JPEG_AC_T0_R1_137 0x772
00969 #define REG_JPEG_AC_T0_R1_138 0x774
00970 #define REG_JPEG_AC_T0_R1_139 0x776
00971 #define REG_JPEG_AC_T0_R1_140 0x778
00972 #define REG_JPEG_AC_T0_R1_141 0x77a
00973 #define REG_JPEG_AC_T0_R1_142 0x77c
00974 #define REG_JPEG_AC_T0_R1_143 0x77e
00975 #define REG_JPEG_AC_T0_R1_144 0x780
00976 #define REG_JPEG_AC_T0_R1_145 0x782
00977 #define REG_JPEG_AC_T0_R1_146 0x784
00978 #define REG_JPEG_AC_T0_R1_147 0x786
00979 #define REG_JPEG_AC_T0_R1_148 0x788
00980 #define REG_JPEG_AC_T0_R1_149 0x78a
00981 #define REG_JPEG_AC_T0_R1_150 0x78c
00982 #define REG_JPEG_AC_T0_R1_151 0x78e
00983 #define REG_JPEG_AC_T0_R1_152 0x790
00984 #define REG_JPEG_AC_T0_R1_153 0x792
00985 #define REG_JPEG_AC_T0_R1_154 0x794
00986 #define REG_JPEG_AC_T0_R1_155 0x796
00987 #define REG_JPEG_AC_T0_R1_156 0x798
00988 #define REG_JPEG_AC_T0_R1_157 0x79a
00989 #define REG_JPEG_AC_T0_R1_158 0x79c
00990 #define REG_JPEG_AC_T0_R1_159 0x79e
00991 #define REG_JPEG_AC_T0_R1_160 0x7a0
00992 #define REG_JPEG_AC_T0_R1_161 0x7a2
00993
00994 #define REG_JPEG_DC_T1_R0_00 0x800
00995 #define REG_JPEG_DC_T1_R0_01 0x802
00996 #define REG_JPEG_DC_T1_R0_02 0x804
00997 #define REG_JPEG_DC_T1_R0_03 0x806
00998 #define REG_JPEG_DC_T1_R0_04 0x808
00999 #define REG_JPEG_DC_T1_R0_05 0x80a
01000 #define REG_JPEG_DC_T1_R0_06 0x80c
01001 #define REG_JPEG_DC_T1_R0_07 0x80e
01002 #define REG_JPEG_DC_T1_R0_08 0x810
01003 #define REG_JPEG_DC_T1_R0_09 0x812
01004 #define REG_JPEG_DC_T1_R0_10 0x814
01005 #define REG_JPEG_DC_T1_R0_11 0x816
01006 #define REG_JPEG_DC_T1_R0_12 0x818
01007 #define REG_JPEG_DC_T1_R0_13 0x81a
01008 #define REG_JPEG_DC_T1_R0_14 0x81c
01009 #define REG_JPEG_DC_T1_R0_15 0x81e
01010
01011 #define REG_JPEG_DC_T1_R1_00 0x820
01012 #define REG_JPEG_DC_T1_R1_01 0x822
01013 #define REG_JPEG_DC_T1_R1_02 0x824
01014 #define REG_JPEG_DC_T1_R1_03 0x826
01015 #define REG_JPEG_DC_T1_R1_04 0x828
01016 #define REG_JPEG_DC_T1_R1_05 0x82a
01017 #define REG_JPEG_DC_T1_R1_06 0x82c
01018 #define REG_JPEG_DC_T1_R1_07 0x82e
01019 #define REG_JPEG_DC_T1_R1_08 0x830
01020 #define REG_JPEG_DC_T1_R1_09 0x832
01021 #define REG_JPEG_DC_T1_R1_10 0x834
01022 #define REG_JPEG_DC_T1_R1_11 0x836
01023
01024 #define REG_JPEG_AC_T1_R0_00 0x840
01025 #define REG_JPEG_AC_T1_R0_01 0x842
01026 #define REG_JPEG_AC_T1_R0_02 0x844
01027 #define REG_JPEG_AC_T1_R0_03 0x846
01028 #define REG_JPEG_AC_T1_R0_04 0x848
01029 #define REG_JPEG_AC_T1_R0_05 0x84a
01030 #define REG_JPEG_AC_T1_R0_06 0x84c
01031 #define REG_JPEG_AC_T1_R0_07 0x84e
01032 #define REG_JPEG_AC_T1_R0_08 0x850
01033 #define REG_JPEG_AC_T1_R0_09 0x852
01034 #define REG_JPEG_AC_T1_R0_10 0x854
01035 #define REG_JPEG_AC_T1_R0_11 0x856
01036 #define REG_JPEG_AC_T1_R0_12 0x858
01037 #define REG_JPEG_AC_T1_R0_13 0x85a
01038 #define REG_JPEG_AC_T1_R0_14 0x85c
01039 #define REG_JPEG_AC_T1_R0_15 0x85e
01040
01041 #define REG_JPEG_AC_T1_R1_00 0x860
01042 #define REG_JPEG_AC_T1_R1_01 0x862
01043 #define REG_JPEG_AC_T1_R1_02 0x864
01044 #define REG_JPEG_AC_T1_R1_03 0x866
01045 #define REG_JPEG_AC_T1_R1_04 0x868
01046 #define REG_JPEG_AC_T1_R1_05 0x86a
01047 #define REG_JPEG_AC_T1_R1_06 0x86c
01048 #define REG_JPEG_AC_T1_R1_07 0x86e
01049 #define REG_JPEG_AC_T1_R1_08 0x870
01050 #define REG_JPEG_AC_T1_R1_09 0x872
01051 #define REG_JPEG_AC_T1_R1_10 0x874
01052 #define REG_JPEG_AC_T1_R1_11 0x876
01053 #define REG_JPEG_AC_T1_R1_12 0x878
01054 #define REG_JPEG_AC_T1_R1_13 0x87a
01055 #define REG_JPEG_AC_T1_R1_14 0x87c
01056 #define REG_JPEG_AC_T1_R1_15 0x87e
01057 #define REG_JPEG_AC_T1_R1_16 0x880
01058 #define REG_JPEG_AC_T1_R1_17 0x882
01059 #define REG_JPEG_AC_T1_R1_18 0x884
01060 #define REG_JPEG_AC_T1_R1_19 0x886
01061 #define REG_JPEG_AC_T1_R1_20 0x888
01062 #define REG_JPEG_AC_T1_R1_21 0x88a
01063 #define REG_JPEG_AC_T1_R1_22 0x88c
01064 #define REG_JPEG_AC_T1_R1_23 0x88e
01065 #define REG_JPEG_AC_T1_R1_24 0x890
01066 #define REG_JPEG_AC_T1_R1_25 0x892
01067 #define REG_JPEG_AC_T1_R1_26 0x894
01068 #define REG_JPEG_AC_T1_R1_27 0x896
01069 #define REG_JPEG_AC_T1_R1_28 0x898
01070 #define REG_JPEG_AC_T1_R1_29 0x89a
01071 #define REG_JPEG_AC_T1_R1_30 0x89c
01072 #define REG_JPEG_AC_T1_R1_31 0x89e
01073 #define REG_JPEG_AC_T1_R1_32 0x8a0
01074 #define REG_JPEG_AC_T1_R1_33 0x8a2
01075 #define REG_JPEG_AC_T1_R1_34 0x8a4
01076 #define REG_JPEG_AC_T1_R1_35 0x8a6
01077 #define REG_JPEG_AC_T1_R1_36 0x8a8
01078 #define REG_JPEG_AC_T1_R1_37 0x8aa
01079 #define REG_JPEG_AC_T1_R1_38 0x8ac
01080 #define REG_JPEG_AC_T1_R1_39 0x8ae
01081 #define REG_JPEG_AC_T1_R1_40 0x8b0
01082 #define REG_JPEG_AC_T1_R1_41 0x8b2
01083 #define REG_JPEG_AC_T1_R1_42 0x8b4
01084 #define REG_JPEG_AC_T1_R1_43 0x8b6
01085 #define REG_JPEG_AC_T1_R1_44 0x8b8
01086 #define REG_JPEG_AC_T1_R1_45 0x8ba
01087 #define REG_JPEG_AC_T1_R1_46 0x8bc
01088 #define REG_JPEG_AC_T1_R1_47 0x8be
01089 #define REG_JPEG_AC_T1_R1_48 0x8c0
01090 #define REG_JPEG_AC_T1_R1_49 0x8c2
01091 #define REG_JPEG_AC_T1_R1_50 0x8c4
01092 #define REG_JPEG_AC_T1_R1_51 0x8c6
01093 #define REG_JPEG_AC_T1_R1_52 0x8c8
01094 #define REG_JPEG_AC_T1_R1_53 0x8ca
01095 #define REG_JPEG_AC_T1_R1_54 0x8cc
01096 #define REG_JPEG_AC_T1_R1_55 0x8ce
01097 #define REG_JPEG_AC_T1_R1_56 0x8d0
01098 #define REG_JPEG_AC_T1_R1_57 0x8d2
01099 #define REG_JPEG_AC_T1_R1_58 0x8d4
01100 #define REG_JPEG_AC_T1_R1_59 0x8d6
01101 #define REG_JPEG_AC_T1_R1_60 0x8d8
01102 #define REG_JPEG_AC_T1_R1_61 0x8da
01103 #define REG_JPEG_AC_T1_R1_62 0x8dc
01104 #define REG_JPEG_AC_T1_R1_63 0x8de
01105 #define REG_JPEG_AC_T1_R1_64 0x8e0
01106 #define REG_JPEG_AC_T1_R1_65 0x8e2
01107 #define REG_JPEG_AC_T1_R1_66 0x8e4
01108 #define REG_JPEG_AC_T1_R1_67 0x8e6
01109 #define REG_JPEG_AC_T1_R1_68 0x8e8
01110 #define REG_JPEG_AC_T1_R1_69 0x8ea
01111 #define REG_JPEG_AC_T1_R1_70 0x8ec
01112 #define REG_JPEG_AC_T1_R1_71 0x8ee
01113 #define REG_JPEG_AC_T1_R1_72 0x8f0
01114 #define REG_JPEG_AC_T1_R1_73 0x8f2
01115 #define REG_JPEG_AC_T1_R1_74 0x8f4
01116 #define REG_JPEG_AC_T1_R1_75 0x8f6
01117 #define REG_JPEG_AC_T1_R1_76 0x8f8
01118 #define REG_JPEG_AC_T1_R1_77 0x8fa
01119 #define REG_JPEG_AC_T1_R1_78 0x8fc
01120 #define REG_JPEG_AC_T1_R1_79 0x8fe
01121 #define REG_JPEG_AC_T1_R1_80 0x900
01122 #define REG_JPEG_AC_T1_R1_81 0x902
01123 #define REG_JPEG_AC_T1_R1_82 0x904
01124 #define REG_JPEG_AC_T1_R1_83 0x906
01125 #define REG_JPEG_AC_T1_R1_84 0x908
01126 #define REG_JPEG_AC_T1_R1_85 0x90a
01127 #define REG_JPEG_AC_T1_R1_86 0x90c
01128 #define REG_JPEG_AC_T1_R1_87 0x90e
01129 #define REG_JPEG_AC_T1_R1_88 0x910
01130 #define REG_JPEG_AC_T1_R1_89 0x912
01131 #define REG_JPEG_AC_T1_R1_90 0x914
01132 #define REG_JPEG_AC_T1_R1_91 0x916
01133 #define REG_JPEG_AC_T1_R1_92 0x918
01134 #define REG_JPEG_AC_T1_R1_93 0x91a
01135 #define REG_JPEG_AC_T1_R1_94 0x91c
01136 #define REG_JPEG_AC_T1_R1_95 0x91e
01137 #define REG_JPEG_AC_T1_R1_96 0x920
01138 #define REG_JPEG_AC_T1_R1_97 0x922
01139 #define REG_JPEG_AC_T1_R1_98 0x924
01140 #define REG_JPEG_AC_T1_R1_99 0x926
01141 #define REG_JPEG_AC_T1_R1_100 0x928
01142 #define REG_JPEG_AC_T1_R1_101 0x92a
01143 #define REG_JPEG_AC_T1_R1_102 0x92c
01144 #define REG_JPEG_AC_T1_R1_103 0x92e
01145 #define REG_JPEG_AC_T1_R1_104 0x930
01146 #define REG_JPEG_AC_T1_R1_105 0x932
01147 #define REG_JPEG_AC_T1_R1_106 0x934
01148 #define REG_JPEG_AC_T1_R1_107 0x936
01149 #define REG_JPEG_AC_T1_R1_108 0x938
01150 #define REG_JPEG_AC_T1_R1_109 0x93a
01151 #define REG_JPEG_AC_T1_R1_110 0x93c
01152 #define REG_JPEG_AC_T1_R1_111 0x93e
01153 #define REG_JPEG_AC_T1_R1_112 0x940
01154 #define REG_JPEG_AC_T1_R1_113 0x942
01155 #define REG_JPEG_AC_T1_R1_114 0x944
01156 #define REG_JPEG_AC_T1_R1_115 0x946
01157 #define REG_JPEG_AC_T1_R1_116 0x948
01158 #define REG_JPEG_AC_T1_R1_117 0x94a
01159 #define REG_JPEG_AC_T1_R1_118 0x94c
01160 #define REG_JPEG_AC_T1_R1_119 0x94e
01161 #define REG_JPEG_AC_T1_R1_120 0x950
01162 #define REG_JPEG_AC_T1_R1_121 0x952
01163 #define REG_JPEG_AC_T1_R1_122 0x954
01164 #define REG_JPEG_AC_T1_R1_123 0x956
01165 #define REG_JPEG_AC_T1_R1_124 0x958
01166 #define REG_JPEG_AC_T1_R1_125 0x95a
01167 #define REG_JPEG_AC_T1_R1_126 0x95c
01168 #define REG_JPEG_AC_T1_R1_127 0x95e
01169 #define REG_JPEG_AC_T1_R1_128 0x960
01170 #define REG_JPEG_AC_T1_R1_129 0x962
01171 #define REG_JPEG_AC_T1_R1_130 0x964
01172 #define REG_JPEG_AC_T1_R1_131 0x966
01173 #define REG_JPEG_AC_T1_R1_132 0x968
01174 #define REG_JPEG_AC_T1_R1_133 0x96a
01175 #define REG_JPEG_AC_T1_R1_134 0x96c
01176 #define REG_JPEG_AC_T1_R1_135 0x96e
01177 #define REG_JPEG_AC_T1_R1_136 0x970
01178 #define REG_JPEG_AC_T1_R1_137 0x972
01179 #define REG_JPEG_AC_T1_R1_138 0x974
01180 #define REG_JPEG_AC_T1_R1_139 0x976
01181 #define REG_JPEG_AC_T1_R1_140 0x978
01182 #define REG_JPEG_AC_T1_R1_141 0x97a
01183 #define REG_JPEG_AC_T1_R1_142 0x97c
01184 #define REG_JPEG_AC_T1_R1_143 0x97e
01185 #define REG_JPEG_AC_T1_R1_144 0x980
01186 #define REG_JPEG_AC_T1_R1_145 0x982
01187 #define REG_JPEG_AC_T1_R1_146 0x984
01188 #define REG_JPEG_AC_T1_R1_147 0x986
01189 #define REG_JPEG_AC_T1_R1_148 0x988
01190 #define REG_JPEG_AC_T1_R1_149 0x98a
01191 #define REG_JPEG_AC_T1_R1_150 0x98c
01192 #define REG_JPEG_AC_T1_R1_151 0x98e
01193 #define REG_JPEG_AC_T1_R1_152 0x990
01194 #define REG_JPEG_AC_T1_R1_153 0x992
01195 #define REG_JPEG_AC_T1_R1_154 0x994
01196 #define REG_JPEG_AC_T1_R1_155 0x996
01197 #define REG_JPEG_AC_T1_R1_156 0x998
01198 #define REG_JPEG_AC_T1_R1_157 0x99a
01199 #define REG_JPEG_AC_T1_R1_158 0x99c
01200 #define REG_JPEG_AC_T1_R1_159 0x99e
01201 #define REG_JPEG_AC_T1_R1_160 0x9a0
01202 #define REG_JPEG_AC_T1_R1_161 0x9a2
01203
01204 #define REG_JPEG_QTABLE_CONST_0 0x9b0
01205 #define REG_JPEG_QTABLE_CONST_1 0x9b2
01206 #define REG_JPEG_QTABLE_CONST_2 0x9b4
01207 #define REG_JPEG_QTABLE_CONST_3 0x9b6
01208
01209 #define REG_JPEG_QTABLE0_SAMPLE 0x9b8
01210 #define REG_JPEG_QTABLE1_SAMPLE 0x9bc
01211 #define REG_JPEG_QTABLE2_SAMPLE 0x9c0
01212
01213 #define REG_JPEG_DRI_CONST_0 0x9c4
01214 #define REG_JPEG_DRI_CONST_1 0x9c6
01215 #define REG_JPEG_DRI_CONST_2 0x9c8
01216 #define REG_JPEG_DRI_CONST_3 0x9ca
01217
01218 #define REG_JPEG_SOS_CONST_0 0x9cc
01219 #define REG_JPEG_SOS_CONST_1 0x9ce
01220 #define REG_JPEG_SOS_CONST_2 0x9d0
01221 #define REG_JPEG_SOS_CONST_3 0x9d2
01222 #define REG_JPEG_SOS_CONST_4 0x9d4
01223
01224 #define REG_JPEG_EOI_CONST_0 0x9e4
01225 #define REG_JPEG_EOI_CONST_1 0x9e6
01226 #define REG_JPEG_EOI_CONST_2 0x9e8
01227 #define REG_JPEG_EOI_CONST_3 0x9ea
01228 #define REG_JPEG_EOI_CONST_4 0x9ec
01229
01230 #define REG_JPEG_VERT_PIX_SIZE0 0x9f0
01231 #define REG_JPEG_VERT_PIX_SIZE1 0x9f2
01232 #define REG_JPEG_HORI_PIX_SIZE0 0x9f4
01233 #define REG_JPEG_HORI_PIX_SIZE1 0x9f6
01234 #define REG_JPEG_DRI_CONFIG0 0x9f8
01235 #define REG_JPEG_DRI_CONFIG1 0x9fa
01236
01237 #define REG_DEFINE_END 0xffff
01238
01239 #endif